1. Field of the Invention
The present invention relates to a regulated dc power supply, and more particularly to a switch-mode dc power supply (switching dc power supply) having a control circuit merging in a semiconductor chip so as to form a monolithic integrated circuit (IC), which is highly stable both at light and heavy loads, and a hybrid IC mounting the monolithic IC chip and a semiconductor switching element chip on a same substrate.
2. Description of the Related Art
Traditionally, linear power supplies have been used. However, advances in semiconductor technology have lead to switch-mode dc power supplies, which are smaller and much more efficient compared to linear power supplies. Generally, the switch-mode dc power supply employs a pulse width modulation (PWM) strategy, and a semiconductor switching element is connected to a primary winding of a high-frequency isolation transformer (hereinafter called "the HF transformer"). And an unregulated dc voltage is supplied to the primary winding of the HF transformer. The unregulated dc voltage is converted into an ac voltage by turning the semiconductor switching element fully on or fully off. And the ac voltage at the secondary side of the HF transformer is rectified and smoothed on a secondary side of the HF transformer. The output dc voltage at the secondary side of the HF transformer is regulated by means of feedback control that employs a PWM controller. Then, the obtained regulated dc voltage is applied to the output load.
The dc voltage at secondary side of the switch-mode dc power supply fluctuates continuously in accordance with the load state. For instance, when the load is heavy, the secondary side dc voltage falls with respect to the rated output voltage, and when the load is light, the secondary side dc voltage rises. For this reason, the ON/OFF periods of the semiconductor switching element are controlled by using a negative-feedback control system, while detecting the state of the secondary side dc voltage, so that the rated output voltage is always obtained on the secondary side of the HF transformer. That is, when the load is heavy, the ON state pulse width (hereinafter called "the pulse duration") of the current flowing through the semiconductor switching element is widened to increase the amount of current induced at the secondary side of the HF transformer so as to raise the dc voltage nearer to the rated voltage. On the contrary, when the load is light, the pulse duration of the current flowing through the semiconductor switching element is made narrower to reduce the amount of current induced at the secondary side of the HF transformer, so as to reduce the dc voltage nearer to the rated output voltage. And thereby, the stable and constant dc voltage is implemented.
FIG. 1A is a schematic configuration of a switch-mode dc power supply according to a voltage-mode control scheme. As shown in FIG. 1A, the switch-mode dc power supply in the voltage-mode control scheme has a rectifier/smoothing circuit 3. The input terminals 1 and 2 of the rectifier/smoothing circuit 3 are connected to a commercial ac power line. A first series circuit 6 has a primary winding 5 of a HF transformer 4 and a MOS transistor Q1, and is connected between the output terminals 3a and 3b of the rectifier/smoothing circuit 3. Furthermore, the HF transformer 4 has an auxiliary winding 7, which is connected to a diode 8 and a capacitor 9. A power for driving a control circuit explained later is obtained at the connection point A of the capacitor 9 and the cathode terminals of the diode 8. Furthermore, one end of a resistor R2 connects to the connection point A, and the other end of the resistor R2 connects to the end 5a of the primary winding 5 of the HF transformer 4.
On the secondary side of the HF transformer 4, a diode 11 and a capacitor 12 are connected to a secondary winding 10 of the HF transformer 4. And one terminal 14 of a load 13 is connected to the connection point of the cathode terminals of the diode 11 and the capacitor 12. A detection point C is provided at the connection point on the secondary side of the HF transformer 4. And a detection circuit 18 is provided for detecting dc voltage obtained on the secondary side of the HF transformer 4 from this detection point C via an input terminal 18a.
Moreover, a control circuit 20 is provided on the primary side of the HF transformer 4 to generate a triangular reference voltage so as to output a control signal of a predetermined duty ratio (hereinafter called "drive signal"). The drive signal is fed to a gate electrode G of a power MOS FET (hereinafter called simply "MOStransistor Q1") based on the voltage detected by the detection circuit 18, and thereby driving the MOStransistor Q1 between the ON and OFF states.
The control circuit 20 has an input terminal 20a which receives a driving power from the connection point A, an input terminal 20b connected to the output terminal 18b of the detection circuit 18, an output terminal 20c and an output terminal 20d. The output terminal 20c sends the drive signal to the gate electrode G of the MOS transistor Q1. And the output terminal 20d is jointly connected to the source electrode S of the MOS transistor Q1, the other end of the capacitor 9, the other end 7b of the auxiliary winding 7, the other output terminal 3b of the rectifier/smoothing circuit 3, and ground.
As shown in FIG. 1B, the control circuit 20 has a regulator 21, an oscillator (OSC) 22, and resistors R3 and R4 for dividing the reference voltage from the regulator 21 and obtaining a control voltage V7 at a voltage-division point B. The regulator 21 generates a regulated reference voltage using the driving power from the input terminal 20a. The oscillator (OSC) 22 outputs a triangular reference voltage V8 and a rectangular pulse wave V9 (hereinafter called "the rectangular synchronizing pulse signal V9). The triangular reference voltage V8 has a triangular waveform, repeating a pattern of rising linearly with time from the lowest to the highest voltage, and then falling linearly with time to the lowest voltage. And the rectangular synchronizing pulse signal V9 has a rectangular waveform for determining dead time of a driver (explained later) in synchronism with the triangular reference voltage V8.
The control circuit 20 further has a comparator 23, a flip-flop 24, a NOR gate 25 and a driver 26. The comparator 23 outputs a signal V10 based on a comparison of the control voltage V7 and the triangular reference voltage V8 from the oscillator 22. The flip-flop 24 inputs the signal V10 from the comparator 23 to a reset terminal R (hereinafter called "R terminal"), and input the rectangular synchronizing pulse signal V9 from the oscillator 22 to a set terminal S (hereinafter called "S terminal"). Similarly, and obtains a logical output signal of these at an output terminal, or a "Q-bar" terminal. The NOR gate 25 receives the rectangular synchronizing pulse signal V9 and the logical output signal from the flip-flop 24, and outputs a logical NOR of these. The driver 26 outputs to the gate electrode G a drive signal V11 for driving the MOS transistor Q1, based on the logical NOR from the NOR gate 25.
On the other hand, as shown in FIG. 1B, the detection circuit 18 has resistors R5 and R6 and a differential amplifier 28. Through the resistors R5 and R6, the dc voltage at the detection point C in the secondary side of the HF transformer 4 is obtained at a voltage-division point D. And the output level of the differential amplifier 28 controls an optical coupler 29, based on the difference between the dc voltage at the voltage-division point D and a reference voltage 27. Furthermore, the collector electrode of a phototransistor in the optical coupler 29 is connected via the input terminal 20b of the control circuit 20 to the voltage-division point B between the resistors R3 and R4.
That is, the dc voltage Vout at the detection point C on the secondary side of the HF transformer 4 is detected, and is inputted to the detection circuit 18 as a feedback signal. And, the detection circuit 18 adjusts the control voltage V7 depending on the difference between the voltage level of this feedback signal and the reference voltage 27.
FIG. 1C is a timing chart explaining the operation of the switch-mode dc power supply by the voltage-mode control scheme. When the input terminals 1 and 2 are connected to the commercial ac power line, the rectifier/smoothing circuit 3 rectifies and smoothes the ac current. Then, the dc current obtained by the rectifier/smoothing circuit 3 is applied to a second series circuit, including the resistor R2 and the capacitor 9, and a control power at a predetermined voltage is obtained at the connection point A. The control power is supplied to the control circuit 20 via the input terminal 20a. When the control power is supplied, the control circuit 20 commences operation, and generates a sequence of pulses to the primary winding 5 of the HF transformer 4 by turning MOStransistor Q1 on and off. In addition, the control circuit 20 induces another sequence of pulses in the secondary winding 10 of the HF transformer 4 based on the winding turns ratio of the two windings, thereby obtaining a rectified and smoothed dc voltage from the diode 11 and the capacitor 12.
The regulator 21 of the control circuit 20 obtains a predetermined dc voltage from the power supply for driving, and supplies it to a first series circuit including the oscillator 22 and the resistors R3 and R4. When the oscillator 22 receives the dc voltage, it sends the triangular reference voltage V8 at a predetermined frequency, as shown in FIG. 1C, to the comparator 23. And the oscillator 22 outputs the rectangular synchronizing pulse signal V9 in order to determine a dead time for the driver 26 in synchronism with the triangular reference voltage V8.
The rectangular synchronizing pulse signal V9 holds the "H" level while the triangular reference voltage V8 is decreasing from the maximum value to the minimum value. Furthermore, the potential level of the control voltage V7 at the voltage-division point B fluctuates (when the load is heavy or light) depending on the voltage detected by the detection circuit 18.
The comparator 23 compares the potential levels of the control voltage V7 and the triangular reference voltage V8, and transmits an output signal V10 to the R terminal of the flip-flop 24. The output signal V10 keeps the "H" level during the period in which the potential level of the triangular reference voltage V8 is exceeding the potential level of the control voltage V7.
As a consequence, when the rectangular synchronizing pulse signal V9 and the output signal V10 are at the "L" level, the flip-flop 24 outputs a signal (not shown) from the "Q-bar" terminal at the "H" level. And, when the rectangular synchronizing pulse signal V9 is at the "L" level and the output signal V10 is at the "H" level, the flip-flop 24 outputs an L-level output signal at the "Q-bar" terminal. Furthermore, when the rectangular synchronizing pulse signal V9 is at the "H" level and the output signal V10 is at the "H" level, an "H" level signal is outputted from the "Q-bar" terminal.
The signal output from the flip-flop 24 is inverted by the NOR gate 25 to generate an inverted signal (not shown), which is sent to the driver 26. When the driver 26 receives the signal from the NOR gate 25, it transmits the drive signal V11 shown in FIG. 1C to the gate electrode G of the MOS transistor Q1.
As shown in FIG. 1C, the drive signal V11 is the "H" level, when the triangular reference voltage V8 is at the lowest value. And the drive signal V11 keeps the "H" level, when the potential level of the triangular reference voltage V8 is increasing from the lowest value to reach the potential level of the control voltage V7. And the drive signal V11 becomes the "L" level, when the dc voltage of the secondary side of the HF transformer 4 exceeds the reference voltage 27 so that the output signal V10 from the comparator 23 raise to the "H" level. In this way, the drive signal V11 repeatedly switches between the "H" level and the "L" level.
The MOS transistor Q1 performs the switching operation with the charge and discharge of gate input capacitance. And the pulse duration of the drive signal V11 for driving the MOS transistor Q1 is controlled by the comparison of the potential levels of the triangular reference voltage V8 and the control voltage V7. Hence, the current I4 flowing through MOS transistor Q1 manifests a stable current waveform I4 with light load as shown in FIG. 1C.
However, with heavy load, since the pulse duration of the drive signal V11 is determined by comparing the triangular reference voltage V8 and the control voltage V7, the peak current I4 flowing through MOS transistor Q1 becomes greater than that for light load. In such a state, an oscillation shown in FIG. 1C is especially liable to occur. And there have been many cases when this oscillation state continues across two or more cycles, influencing the secondary side dc voltage, which forms the waveform of the output power, and resulting in unstable operation. In such a case, the phase must be corrected in the control circuit.
Like this way, even when the input/output state of the switch-mode power supply is not fluctuating, in the voltage-mode control scheme, an oscillation having different current peaks for each cycles is likely to occur in the current 14 flowing through the MOS transistor Q1, as shown in FIG. 1C. This is because the voltage-mode control scheme regulates the current flowing through MOS transistor Q1 by adjusting the ON period of the MOS transistor Q1, based on the comparison between the control voltage V7 and the triangular waveform voltage V8, and thereby controls the output voltage. Here, the control voltage V7 is the feedback voltage signal obtained on the secondary side of the HF transformer 4. When such oscillation occurs, it is necessary to correct the phase of the control circuit, but there is a problem that it takes time to investigate, consider or redesign the circuit for correcting the phase. Furthermore, even when an enough time has been wasted for the countermeasure against the oscillation, it is not always possible to correct the phase completely.